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N08L63W2A
Functional Block Diagram
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A18
Page
Address
Decode
Logic
32K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
I/O0 - I/O7
I/O8 - I/O15
CE1
CE2
W E
OE
Control
Logic
U B
LB
Functional Description
L
CE1
H
X
X
L
L
L
CE2
X
L
X
H
H
H
WE
X
X
X
L
H
H
OE
X
X
X
X 3
L
H
UB
X
X
H
L 1
1
L 1
LB
X
X
H
L 1
L 1
L 1
I/O 0 - I/O 151
High Z
High Z
High Z
Data In
Data Out
High Z
MODE
Standby 2
Standby 2
Standby 2
Write 3
Read
Active
POWER
Standby
Standby
Standby
Active
Active
Active
1. When UB and LB are in select mode (low), I/O 0 - I/O 15 are affected as shown. When LB only is in the select mode only I/O 0 - I/O 7
are affected as shown. When UB is in the select mode only I/O 8 - I/O 15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance 1
Item
Input Capacitance
I/O Capacitance
Symbol
C IN
C I/O
Test Condition
V IN = 0V, f = 1 MHz, T A = 25 o C
V IN = 0V, f = 1 MHz, T A = 25 o C
Min
Max
8
8
Unit
pF
pF
1. These parameters are verified in device characterization and are not 100% tested
Rev. 8 | Page 2 of 10 | www.onsemi.com
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